Agilent Technologies launches integrated PCI Express 3.0 transmitter test software

Telecom Lead America: Test and Measurement solutions
provider Agilent Technologies has launched its integrated PCI Express (PCIe)
3.0 receiver test calibration and transmitter test software.


The software is designed to provide an integrated
environment for calibrating the stressed voltage and stressed receiver eye
using an Agilent J-BERT bit error-ratio tester, an Agilent 90000A-, Q- or
X-Series oscilloscope, an Agilent pulse function generator and Agilent PCI
Express 3.0 calibration test channels.


Sigi Gross, vice president of Agilent’s Electronic Test
Division, said its expertise in receiver and transmitter test allows Agilent to
be the first vendor to offer tools that integrate the functions of BERTs,
oscilloscopes and signal generators to help customers accomplish their receiver
testing requirements for PCI Express 3.0 devices and systems.


Moreover, Agilent Technologies’ N5393C Option 004 PCI
Express 3.0 receiver test calibration software provides a receiver signal calibration
test suite that allows engineers to set up a J-BERT N4903B bit error-ratio
tester for performing PCI Express 3.0 jitter tolerance testing under the PCIe
3.0 Base specification.


Agilent said by automating the calibration of the bit
error-ratio test signal, engineers save valuable test time and are able to
achieve a consistent and reliable stressed eye signal, ensuring their PCIe 3.0
devices meet the requirements of the specification for jitter and voltage
stress levels.


PCI Express technology is used in high-performance
server, workstation and graphics-intensive desktop applications. The PCIe 3.0
standard, for operation at 8 gigabits per second, requires that PCIe
3.0-compliant devices support a robust receiver equalizer capable of opening what
would otherwise be deemed a closed-eye signal.


Without the software, the procedure for calibrating the
output of a bit error-ratio tester to meet the PCIe 3.0 testing requirements is
tedious and complicated, as random jitter, sinusoidal jitter, and common-mode
and differential-mode noise must all be applied simultaneously.


Al Yanes, PCI-SIG president and chairman, said an
important objective of the PCI-SIG is achieving full interoperability at 8
GT/s, and validation and delivery of fully compliant PCIe 3.0 receivers and
transmitters is critical to achieving that objective.


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