Cadence announces new protocol and memory model verification IP


Cadence Design Systems announced new protocol and memory
model verification IP (VIP) that will accelerate the adoption of the latest
mobile standards.


Through collaboration with system and semiconductor
companies, and standards bodies, Cadence is delivering VIP at a very early
stage in many cases, ahead of the final specification helping mobile SoC and
system manufacturers to be first to market with increasingly feature-rich
mobile devices, such as smartphones and tablets.


“The need for increased computing power and
sophisticated video, audio and storage on mobile devices has given rise to new
standards that improve performance and power, while reducing development time
and cost,” said Ziv Binyamini, corporate vice president, research and
development, System Realization Group at Cadence.


“In order to leverage these standards, our customers
need solutions that can accurately test the functionality of their design and
ensure manufacturing success. Our extensive protocol expertise, combined with
our track record of effectively verifying thousands of designs for over a
decade, gives customers a proven path to success in the mobile market,”
Binyamini added.


Cadence further expanded its VIP
offering for mobile applications with support for the following standards:


LPDDR3: This low-power version of the pervasive DDR3
memory standard enables customers to meet the high bandwidth and power
efficiency requirements of mobile systems.


MIPI CSI-3: Providing an advanced processor-to-camera
sensor interface, MIPI CSI-3 enables mobile devices to deliver the bandwidth
required to enable high resolution video and 3D.


MIPI Low Latency Interface (LLI): This interface cuts
mobile device production cost by allowing DRAM memory sharing between multiple


USB 3.0 On-The-Go (OTG): Providing 10x the performance of
the previous USB specification, USB 3.0 OTG allows consumers to rapidly
transfer data, such as video and audio content, as well as quickly and
effortlessly charge devices.


Universal Flash Storage (UFS): A common flash storage specification
for mobile devices, UFS, a JEDEC standard, is designed to bring higher data
transfer speed and increased reliability to flash memory storage.


eMMC4.5: Designed for secure, yet flexible program code
and data storage, eMMC4.5, a JEDEC standard, enables high bandwidth, low
pin-count solutions that simplify system design.


cJTAG: With its support for reduced pin count, power
management and simplified multichip debug, cJTAG enables efficient testing of
mobile devices, a key requirement for delivering high volume, high quality
mobile devices.


Cadence recently announced that Giantec Semiconductor has
the Cadence Virtuoso unified custom/analog (IC6.1) and Encounter unified
digital flows for production of its mixed-signal chips.


Giantec recently deployed the Cadence technology to design and
tape out a memory product for a low-power micro-controller used in its smart
cards, intelligent energy meters and consumer products.


By Team
[email protected]