Vitesse Semiconductor, a provider of advanced IC
solutions for Carrier and Enterprise networks, and Aliathon announced that
Aliathon will license Vitesse’s portfolio of 40G and 100G hard decision
enhanced Forward Error Correction (eFEC) cores for its FPGA and ASSP solutions
aimed at emerging Optical Transport Network (OTN) applications.

Widely applied in fiber optic communications, eFEC
reduces bit error rate in typically noisy signal environments. Developing
cost-effective, improved signal-to-noise ratio solutions becomes a significant
challenge as metro and long-haul networks transition up to 100G data rates and
beyond.

Vitesse
solves this issue with its patented Continuously Interleaved BCH (CI-BCH) eFEC code which offers the highest
performing hard decision eFEC available today and is the industry’s only eFEC
implementable in FPGA form at 100G.

With optical networks rapidly evolving to accommodate
growing bandwidth demands, service providers are focused on lower cost and
power per bit in their metro and long-haul 100G systems,” said Steve Perna,
vice president of product marketing at Vitesse.

Vitesse’s CI-BCH eFEC technology enables 40G and 100G
backbones to operate over longer spans with lower power, lower cost, and lower
latency. We are excited to add Aliathon to the growing ecosystem of OEMs, ASSP
and FPGA solution providers using CI-BCH technology to implement high-density
40G and 100G Optical Transport solutions,” Perna added.

Providing industry-leading eFEC technology is a critical
component in Aliathon’s OTN strategy. Part of Aliathon’s value to our clients
is rapidly adapting to new requirements in the OTN network. Working with
today’s leader in OTN eFEC technology is testament to that fact,” said Alan
McDade, commercial director at Aliathon.

The combination of Aliathon’s framing, mapping and
muxing technology for OTN with the Vitesse eFEC offers our clients a flexible,
feature rich, high performance, cost effective and power efficient solution.
Aliathon’s intention is to tightly couple Vitesse’s technology with our own and
roll out a range of 100G OTN products throughout Q4-2011,” McDade added.

The Vitesse 40G/100G eFEC core portfolio is based on
Vitesse’s patented and industry-leading CI-BCH eFEC technology. CI-BCH
represents a breakthrough in block coding forward error correction technology
necessary for optimal signal-to-noise ratio at these high data rates. Major
advantages of the CI-BCH eFEC code include:

The CI-BCH eFEC code has ability to optionally configure
to tradeoff coding gain for reduced eFEC decoder latency in sensitive
applications, and to occupy the lowest device resources of any eFEC code in the
marketplace.

The 100G 7 percent and 20 percent overhead ratio cores
occupy only 27 percent and 54 percent of available Lookup Table (LUT) resources
in a Xilinx Virtex 6 FPGA, respectively, meaning that 100G OTN Muxponder and
Transponder solutions can be created in a single FPGA. The 7 percent and 20
percent coding overhead versions provide up to 9.35dB and 10.5dB NECG,
respectively.

At 100G operation and 7 percent overhead ratio, the
Vitesse CI-BCH-3 three error correcting eFEC core delivers 9.35dB NECG at an
output bit error rate of 1x10E-15 and <10us decoder latency, better
performance than any existing 7 percent overhead G.975.1 FEC cores on the
market.

For 100G operation and 20 percent overhead ratio, the
Vitesse CI-BCH-4 four error correcting eFEC core delivers up to 10.5dB NECG at
an output bit error rate of 1x10E-15 and <10us decoder latency.

By Telecomlead.com Team
[email protected]